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Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , and . SLIP@DAC, page 1:1-1:8. ACM, (2018)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)Optimality study of resource binding with multi-Vdds., , , and . DAC, page 580-585. ACM, (2006)Throughput-oriented kernel porting onto FPGAs., , , , and . DAC, page 11:1-11:10. ACM, (2013)C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs., , and . DAC, page 205:1-205:6. ACM, (2014)AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis., , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (3): 46:1-46:30 (September 2023)Performance-driven mapping for CPLD architectures., , , and . FPGA, page 39-47. ACM, (2001)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)A Routing Approach to Reduce Glitches in Low Power FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 235-240 (2010)An Efficient Compiler Framework for Cache Bypassing on GPUs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1677-1690 (2015)