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Disambiguation of "Tamura, Hirotaka"

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3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

, , , , , , , , , , , , , , , , and . ISSCC, page 64-65. IEEE, (2016)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

 

Other publications of authors with the same name

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)Jitter injection for on-chip jitter measurement in PI-based CDRs., , , and . CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE., , , , and . CICC, page 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection., , , , and . CICC, page 1-8. IEEE, (2013)Charge recycling for power reduction in FPGA interconnect., , and . FPL, page 1-8. IEEE, (2013)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS., , , , , , , , , and 8 other author(s). ISSCC, page 360-361. IEEE, (2009)MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA., , , , , and . FPGA, page 155. ACM, (2022)A 3.2Gb/s Semi-Blind-Oversampling CDR., , , and . ISSCC, page 1304-1313. IEEE, (2006)A blind baud-rate ADC-based CDR., , , , and . ISSCC, page 122-123. IEEE, (2013)