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Disambiguation of "Zhuge, Qingfeng"

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Loop scheduling with timing and switching-activity minimization for VLIW DSP.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 165-185 (2006)

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Performance optimization of multiple memory architectures for DSP., , and . ISCAS (5), page 469-472. IEEE, (2002)An Integrated Framework of Design Optimization and Space Minimization for DSP applications., , and . ISCAS (5), page 601-604. IEEE, (2003)Algorithms for Optimally Arranging Multicore Memory Structures., , , , and . EURASIP J. Embed. Syst., (2010)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors., , , , and . ACM Trans. Embed. Comput. Syst., 13 (4): 79:1-79:25 (2014)Loop scheduling with timing and switching-activity minimization for VLIW DSP., , , , and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 165-185 (2006)General loop fusion technique for nested loops considering timing and code size., , , and . CASES, page 190-201. ACM, (2004)Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs., , , , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 121-130. Springer, (2005)Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network., , , , , and . EUC, volume 4096 of Lecture Notes in Computer Science, page 25-34. Springer, (2006)Optimal scheduling to minimize non-volatile memory access time with hardware cache., , , , and . VLSI-SoC, page 131-136. IEEE, (2010)Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors., , , and . IJHPCN, 1 (1/2/3): 4-16 (2004)