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Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.

, , , , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 121-130. Springer, (2005)

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Partitioning and Retiming of Multi-Dimensional Systems., , and . ISCAS, page 227-230. IEEE, (1994)Performance optimization of multiple memory architectures for DSP., , and . ISCAS (5), page 469-472. IEEE, (2002)An Integrated Framework of Design Optimization and Space Minimization for DSP applications., , and . ISCAS (5), page 601-604. IEEE, (2003)Algorithms for Optimally Arranging Multicore Memory Structures., , , , and . EURASIP J. Embed. Syst., (2010)Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (1): 379-389 (2008)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors., , , , and . ACM Trans. Embed. Comput. Syst., 13 (4): 79:1-79:25 (2014)2011 ACM TODAES best paper award., and . ACM Trans. Design Autom. Electr. Syst., 16 (4): 36:1 (2011)Loop scheduling with timing and switching-activity minimization for VLIW DSP., , , , and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 165-185 (2006)Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation., , , , , and . DAC, page 350-355. ACM, (2010)General loop fusion technique for nested loops considering timing and code size., , , and . CASES, page 190-201. ACM, (2004)