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Disambiguation of "Nakajima, Masami"

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A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes.

, , , and . COOL Chips, page 1-3. IEEE Computer Society, (2016)

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Yoshimichi Nakajima

Chikako Nakajima

Nanako Nakajima

Masaki Nakajima

Masami Th Nagatomo

 

Other publications of authors with the same name

A scalable massively parallel processor for real-time image processing., , , , , , , , , and 3 other author(s). ISSCC, page 334-335. IEEE, (2010)Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy., and . ISMVL, page 104-109. IEEE Computer Society, (1996)Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G., , , , , and . CVPR Workshops, page 157-162. IEEE Computer Society, (2011)Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations., and . ISMVL, page 223-230. IEEE Computer Society, (1994)A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (10): 2363-2373 (2011)A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes., , , and . COOL Chips, page 1-3. IEEE Computer Society, (2016)Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor., , , , and . ISMVL, page 43. IEEE Computer Society, (2007)Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations., and . ISMVL, page 283-288. IEEE Computer Society, (1993)Heterogeneous multicore SoC for secure multimedia applications., , , , , , , , , and 5 other author(s). CICC, page 675-678. IEEE, (2008)A 40GOPS 250mW massively parallel processor based on matrix architecture., , , , , , , , , and 2 other author(s). ISSCC, page 1616-1625. IEEE, (2006)