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Disambiguation of "Liao, Hung-Jen"

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A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell.

, , , and . IEEE J. Solid State Circuits, 54 (4): 1152-1160 (2019)

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Chung-Hung Liao

Jen-Jen Lin

Chenkuo Jen

Jen Kurucz

Bingzi Liao

 

Other publications of authors with the same name

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications., , , , , , , , , and 5 other author(s). ISSCC, page 316-317. IEEE, (2013)An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 50 (1): 170-177 (2015)A 4nm 6163-TOPS/W/b $4790-TOPS/mm^2/b$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update., , , , , , , , , and 8 other author(s). ISSCC, page 132-133. IEEE, (2023)A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology., , , , and . VLSI Technology and Circuits, page 110-111. IEEE, (2022)A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 59 (4): 1225-1234 (April 2024)A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications., , , , , , , and . A-SSCC, page 185-188. IEEE, (2016)An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory., , , , , , , , , and 3 other author(s). ISSCC, page 206-208. IEEE, (2011)