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Adaptive Cache Compression for High-Performance Processors.

, и . ISCA, стр. 212-223. IEEE Computer Society, (2004)

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Mohamed Nabil Alaa El-Din

Nour Alaaraj

Alaa Derwiysh

Alaa Fahmy

Alaa Abdellah

 

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Improving DRAM Performance by Parallelizing Refreshes with Accesses., , , , , , и . CoRR, (2017)Improving cache performance using read-write partitioning., , , , и . HPCA, стр. 452-463. IEEE Computer Society, (2014)Improving DRAM performance by parallelizing refreshes with accesses., , , , , , и . HPCA, стр. 356-367. IEEE Computer Society, (2014)Timestamp snooping: an approach for extending SMPs., , , , , , , , , и . ASPLOS, стр. 25-36. ACM Press, (2000)A Case For Asymmetric Processing in Memory., и . IEEE Comput. Archit. Lett., 18 (1): 22-25 (2019)Energy-efficient cache design using variable-strength error-correcting codes., , , , , и . ISCA, стр. 461-472. ACM, (2011)Base-Victim Compression: An Opportunistic Cache Compression Architecture., , и . ISCA, стр. 317-328. IEEE Computer Society, (2016)Adaptive Cache Compression for High-Performance Processors., и . ISCA, стр. 212-223. IEEE Computer Society, (2004)Compresso: Pragmatic Main Memory Compression., , и . MICRO, стр. 546-558. IEEE Computer Society, (2018)Detecting and mitigating data-dependent DRAM failures by exploiting current memory content., , , , , и . MICRO, стр. 27-40. ACM, (2017)