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Disambiguation of "Fujita, Shinobu"

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Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (1): 124-134 (2011)

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Toko Fujita

Buntaro Fujita

Masayuki Fujita

Masakatsu Fujita

Munehisa Fujita

 

Other publications of authors with the same name

Physical random number generator based on MOS structure after soft breakdown., , , , , and . IEEE J. Solid State Circuits, 39 (8): 1375-1377 (2004)Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation., , , , , , and . ISVLSI, page 231-236. IEEE Computer Society, (2006)Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology., , , , , , , and . CoRR, (2017)Patient Context: A New Concept for Gap Model to Understand Patient Satisfaction., and . ICServ, page 151-158. Springer, (2013)Modeling and analysis of circuit performance of ballistic CNFET., , , and . DAC, page 717-722. ACM, (2006)Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (1): 124-134 (2011)D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory., , , , , , , , and . DATE, page 1813-1818. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Novel nonvolatile memory hierarchies to realize "normally-off mobile processors"., , , , and . ASP-DAC, page 6-11. IEEE, (2014)7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)ROM based logic (RBL) design: High-performance and low-power adders., , and . ISCAS, page 796-799. IEEE, (2008)