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Disambiguation of "Xia, Zhengfan"

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Dual-Tap Pipelined-Code-Memory Coded-Exposure-Pixel CMOS Image Sensor for Multi-Exposure Single-Frame Computational Imaging.

, , , , , , , , , , , and . ISSCC, page 102-104. IEEE, (2019)

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Hong Xia

Zhigao Xia

Yingbo Xia

Ye Xia

Ying Xia

 

Other publications of authors with the same name

39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 58 (11): 3150-3163 (November 2023)Efficient and Secure Firmware Update/Rollback Method for Vehicular Devices., , , and . ISPEC, volume 11125 of Lecture Notes in Computer Science, page 455-467. Springer, (2018)Dual-Tap Computational Photography Image Sensor With Per-Pixel Pipelined Digital Memory for Intra-Frame Coded Multi-Exposure., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 54 (11): 3191-3202 (2019)Dual-Tap Pipelined-Code-Memory Coded-Exposure-Pixel CMOS Image Sensor for Multi-Exposure Single-Frame Computational Imaging., , , , , , , , , and 2 other author(s). ISSCC, page 102-104. IEEE, (2019)A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 78-79. IEEE, (2022)Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit., , , and . ISCAS, page 3017-3020. IEEE, (2012)Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates., , , and . IEICE Trans. Electron., 95-C (8): 1434-1443 (2012)Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 619-630 (2015)