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A Passive Switched-Capacitor Finite-Impulse-Response Equalizer., , , и . IEEE J. Solid State Circuits, 42 (2): 400-409 (2007)Analog timing recovery for a noise-predictive decision-feedback equalizer., , и . IEEE J. Solid State Circuits, 38 (2): 338-342 (2003)A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure., , и . IEEE J. Solid State Circuits, 30 (12): 1350-1356 (декабря 1995)An analog background calibration technique for time-interleaved analog-to-digital converters., , , и . IEEE J. Solid State Circuits, 33 (12): 1912-1919 (1998)An analog DFE for disk drives using a mixed-signal integrator., , и . IEEE J. Solid State Circuits, 34 (5): 592-598 (1999)A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS., , и . IEEE J. Solid State Circuits, 31 (9): 1258-1266 (1996)Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier., и . ISCAS, IEEE, (2006)Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter"., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (4): 822 (2005)Background interstage gain calibration technique for pipelined ADCs., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (1): 32-43 (2005)Digital Background Calibration of a Split Current-Steering DAC., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2854-2864 (2019)