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A fuzzy logic controller with reconfigurable, cascadable architecture.

, , and . ICCD, page 474-478. IEEE, (1989)

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A fuzzy logic controller with reconfigurable, cascadable architecture., , and . ICCD, page 474-478. IEEE, (1989)The Omnitest System: A No-Generate, No-Compile, Interactive Test Methodology., and . ITC, page 572-576. IEEE Computer Society, (1989)A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems., , , , , , , , , and 6 other author(s). ISSCC, page 306-307. IEEE, (2013)A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 49 (1): 127-139 (2014)VLSI Fuzzy Chip and Inference Accelerator Board Systems., , , and . ISMVL, page 120-127. IEEE Computer Society, (1991)BioSCAN: A VLSI-Based System for Biosequence Analysis., , , , , , , and . ICCD, page 504-509. IEEE Computer Society, (1991)A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI., , , , , , and . ISSCC, page 370-371. IEEE, (2010)A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching., , , , , , , , , and . CICC, page 1-4. IEEE, (2012)