Inproceedings,
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han, K. Kim, D. Moon, S. Bae, J. Park, K. Ha, J. Lee, S. Doo, J. Shin, C. Shin, K. Oh, D. Hwang, T. Jang, C. Park, K. Park, J. Lee, and J. Choi.ISSCC, page 430-431. IEEE, (2014)
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- conf/isscc/OhCCRLLLKJHKMBP14
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2014
- pages
- 430-431
- publisher
- IEEE
- crossref
- conf/isscc/2014
- ee
- https://doi.org/10.1109/ISSCC.2014.6757500
- isbn
- 978-1-4799-0918-6
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2014.html#OhCCRLLLKJHKMBP14
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%1 conf/isscc/OhCCRLLLKJHKMBP14
%A Oh, Tae-Young
%A Chung, Hoeju
%A Cho, Young-Chul
%A Ryu, Jang-Woo
%A Lee, Kiwon
%A Lee, Changyoung
%A Lee, Jin-Il
%A Kim, Hyoung-Joo
%A Jang, Min-Soo
%A Han, Gong-Heum
%A Kim, Kihan
%A Moon, Daesik
%A Bae, Seung-Jun
%A Park, Joon-Young
%A Ha, Kyung-Soo
%A Lee, Jaewoong
%A Doo, Su-Yeon
%A Shin, Jung-Bum
%A Shin, Chang-Ho
%A Oh, Kiseok
%A Hwang, Doo-Hee
%A Jang, Taeseong
%A Park, Chulsung
%A Park, Kwang-Il
%A Lee, Jung-Bae
%A Choi, Joo-Sun
%B ISSCC
%D 2014
%I IEEE
%K dblp
%P 430-431
%T 25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2014.html#OhCCRLLLKJHKMBP14
%@ 978-1-4799-0918-6
@inproceedings{conf/isscc/OhCCRLLLKJHKMBP14,
added-at = {2022-01-05T00:00:00.000+0100},
author = {Oh, Tae-Young and Chung, Hoeju and Cho, Young-Chul and Ryu, Jang-Woo and Lee, Kiwon and Lee, Changyoung and Lee, Jin-Il and Kim, Hyoung-Joo and Jang, Min-Soo and Han, Gong-Heum and Kim, Kihan and Moon, Daesik and Bae, Seung-Jun and Park, Joon-Young and Ha, Kyung-Soo and Lee, Jaewoong and Doo, Su-Yeon and Shin, Jung-Bum and Shin, Chang-Ho and Oh, Kiseok and Hwang, Doo-Hee and Jang, Taeseong and Park, Chulsung and Park, Kwang-Il and Lee, Jung-Bae and Choi, Joo-Sun},
biburl = {https://www.bibsonomy.org/bibtex/2593c9aa576130b0898b8923e5d197dbd/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2014},
ee = {https://doi.org/10.1109/ISSCC.2014.6757500},
interhash = {06b2f8171c7668b798f5db1d4485eced},
intrahash = {593c9aa576130b0898b8923e5d197dbd},
isbn = {978-1-4799-0918-6},
keywords = {dblp},
pages = {430-431},
publisher = {IEEE},
timestamp = {2024-04-09T20:42:55.000+0200},
title = {25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2014.html#OhCCRLLLKJHKMBP14},
year = 2014
}