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pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han, K. Kim, D. Moon, S. Bae, J. Park, K. Ha, J. Lee, S. Doo, J. Shin, C. Shin, K. Oh, D. Hwang, T. Jang, C. Park, K. Park, J. Lee, and J. Choi. ISSCC, page 430-431. IEEE, (2014)

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Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

Other publications of authors with the same name

HMM and Rule-Based Hybrid Intruder Detection Approach by Synthesizing Decisions of Sensors.K. Kim, K. Park, Y. Jeong, J. Hong, H. Kim, and W. Kim. Int. J. Distributed Sens. Networks, (2013)A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces.B. Kim, L. Kim, K. Park, Y. Jun, and S. Cho. IEEE J. Solid State Circuits, 44 (5): 1522-1530 (2009)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.J. Heo, K. Kim, D. Lee, C. Lee, D. Moon, K. Kim, J. Baek, S. Yoon, H. Yang, K. Kim and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)A DLL with Jitter-Reduction Techniques for DRAM Interfaces.B. Kim, L. Kim, K. Park, Y. Jun, and S. Cho. ISSCC, page 496-497. IEEE, (2007)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.Y. Peng, B. Ku, Y. Park, K. Park, S. Jang, J. Choi, and S. Lim. DAC, page 91:1-91:6. ACM, (2015)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.J. Kim, S. Kang, S. Lee, H. Kim, W. Song, Y. Ro, S. Lee, D. Wang, H. Shin, B. Phuah and 10 other author(s). HCS, page 1-26. IEEE, (2021)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.S. uhn Cha, S. O, H. Shin, S. Hwang, K. Park, S. Jang, J. Choi, G. Jin, Y. Son, H. Cho and 2 other author(s). HPCA, page 61-72. IEEE Computer Society, (2017)A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting.J. Choi, B. Kim, K. Park, and K. Park. ICPP, page 434-443. IEEE Computer Society, (1999)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.S. Bae, Y. Sohn, T. Oh, S. Kim, Y. Yang, D. Kim, S. Kwak, H. Seol, C. Shin, M. Park and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)

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Disambiguation of "Park, Kwang-Il"

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25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

Please choose a person to relate this publication to

Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Park, Kwang-Il"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

Please choose a person to relate this publication to

Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.