Author of the publication

pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han, K. Kim, D. Moon, S. Bae, J. Park, K. Ha, J. Lee, S. Doo, J. Shin, C. Shin, K. Oh, D. Hwang, T. Jang, C. Park, K. Park, J. Lee, and J. Choi. ISSCC, page 430-431. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sun Choi

Im-Joo Choi

Other publications of authors with the same name

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.W. Yun, I. Song, H. Jeoung, H. Choi, S. Lee, J. Kim, C. Kim, J. Choi, S. Jang, and J. Choi. ISSCC, page 1-3. IEEE, (2015)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.Y. Kim, S. Lee, S. Bae, Y. Sohn, J. Lee, J. Choi, H. Park, and J. Sim. ISSCC, page 136-138. IEEE, (2012)An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme.J. Seol, Y. Kim, S. Chung, K. Ha, S. Bae, J. Lee, J. Choi, and L. Kim. ISSCC, page 410-411. IEEE, (2013)Silicon 3D-integration technology and systems.P. Urard, K. Takeuchi, K. Bernstein, H. Hidaka, M. Phan, J. Choi, B. Payne, V. Stojanovic, K. van Berkel, and T. Sakurai. ISSCC, page 510-511. IEEE, (2010)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.Y. Peng, B. Ku, Y. Park, K. Park, S. Jang, J. Choi, and S. Lim. DAC, page 91:1-91:6. ACM, (2015)A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.Y. Bae, J. Park, S. Rhee, S. Ko, Y. Jeong, K. Noh, Y. Son, J. Youn, Y. Chu, H. Cho and 9 other author(s). ISSCC, page 44-46. IEEE, (2012)Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee.J. Choi, and D. Takashima. ISSCC, page 36-37. IEEE, (2012)Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module.S. Jung, J. Seok, H. Yoo, D. Kim, Y. Han, W. Kim, J. Choi, and J. Cho. SoCC, page 343-348. IEEE, (2013)A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.J. Bae, Y. Sohn, S. Bae, K. Park, J. Choi, Y. Jun, J. Sim, and H. Park. CICC, page 1-4. IEEE, (2010)An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.K. Kim, U. Kang, H. Chung, D. Park, W. Kim, Y. Jang, M. Park, H. Lee, J. Kim, J. Sunwoo and 9 other author(s). ISSCC, page 527-536. IEEE, (2006)

BibSonomy

Disambiguation of "Choi, Joo-Sun"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

Please choose a person to relate this publication to

Sun Choi

Sun Choi

Sun Choi

Sun Choi

Im-Joo Choi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Choi, Joo-Sun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

Please choose a person to relate this publication to

Sun Choi

Sun Choi

Sun Choi

Sun Choi

Im-Joo Choi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.