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Disambiguation of "Shin, Jung-Bum"

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25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

, , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 430-431. IEEE, (2014)

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Jung-Bum Shin

Jung-Hyu Shin

Martin Bum

Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen Konzil. Uni München, (2009)
 

Other publications of authors with the same name

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 2055-2063 (2009)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation., , , , , , , , , and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking., , , , , , , , , and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ., , , , , , , , , and 24 other author(s). IEEE J. Solid State Circuits, 58 (1): 279-290 (2023)A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (2): 156-160 (2008)23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices., , , , , , , , , and 26 other author(s). ISSCC, page 394-395. IEEE, (2017)A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL., , , , , , , , , and 14 other author(s). ISSCC, page 412-413. IEEE, (2023)5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (5): 269-273 (2011)