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pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han, K. Kim, D. Moon, S. Bae, J. Park, K. Ha, J. Lee, S. Doo, J. Shin, C. Shin, K. Oh, D. Hwang, T. Jang, C. Park, K. Park, J. Lee, and J. Choi. ISSCC, page 430-431. IEEE, (2014)

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Chul-Woong Cho

Hyun-Chul Cho

Young-Chul Chang

Young Geun Cho

Eun Young Cho

Other publications of authors with the same name

5.7 A 29nW bandgap reference circuit.J. Lee, Y. Ji, S. Choi, Y. Cho, S. Jang, J. Choi, B. Kim, H. Park, and J. Sim. ISSCC, page 1-3. IEEE, (2015)CDISC-compliant clinical trial imaging management system with automatic verification and data Transformation: Focusing on tumor response assessment data in clinical trials.A. Lee, K. Kim, Y. Shin, J. Lee, H. Park, Y. Cho, Y. Ko, Y. Sung, and B. Yoon. J. Biomed. Informatics, (2021)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.S. Bae, K. Park, J. Ihm, H. Song, W. Lee, H. Kim, K. Kim, Y. Park, M. Park, H. Lee and 14 other author(s). IEEE J. Solid State Circuits, 43 (1): 121-131 (2008)A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.H. Yoon, W. Jung, J. Park, J. Byun, H. Jin, H. Cho, Y. Kim, B. Lim, Y. Cho, Y. Choi and 4 other author(s). ESSCIRC, page 463-466. IEEE, (2021)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.J. Ihm, S. Bae, K. Park, H. Song, W. Lee, H. Kim, K. Kim, H. Lee, M. Park, S. Bang and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.I. Yi, S. Bae, M. Chae, S. Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, S. Jang, B. Kim and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Fast cycle-accurate compile based simulator for reconfigurable processor.N. Miniskar, R. Gadde, Y. chul Rams Cho, and S. Kim. ISCAS, page 1-4. IEEE, (2017)Intra mode power saving methodology for CGRA-based reconfigurable processor architectures.N. Miniskar, R. Patil, R. Gadde, Y. chul Rams Cho, S. Kim, and S. Lee. ISCAS, page 714-717. IEEE, (2016)

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Disambiguation of "Cho, Young-Chul"

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25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

Please choose a person to relate this publication to

Chul-Woong Cho

Hyun-Chul Cho

Young-Chul Chang

Young Geun Cho

Eun Young Cho

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cho, Young-Chul"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.

Please choose a person to relate this publication to

Chul-Woong Cho

Hyun-Chul Cho

Young-Chul Chang

Young Geun Cho

Eun Young Cho

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.