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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 314-315. IEEE, (2016)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation., , , , , , , , , и 16 other автор(ы). ISSCC, стр. 430-431. IEEE, (2014)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , и 20 other автор(ы). ISSCC, стр. 434-435. IEEE, (2010)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , и 29 other автор(ы). ISSCC, стр. 382-384. IEEE, (2020)Detecting abnormal behavior of automatic test equipment using autoencoder with event log data., , , , , , , и . Comput. Ind. Eng., (сентября 2023)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking., , , , , , , , , и 39 other автор(ы). ISSCC, стр. 204-206. IEEE, (2018)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW., , , , , , , , , и 19 other автор(ы). ISSCC, стр. 498-500. IEEE, (2011)A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process., , , , , , , , , и 37 other автор(ы). ISSCC, стр. 206-208. IEEE, (2018)