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A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.

I. Kazi, P. Meinerzhagen, P. Gaillardon, D. Sacchetto, A. Burg, and G. Micheli. NEWCAS, page 1-4. IEEE, (2013)

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Davide Pennino

Davide Cadamuro

Davide Batic

Davide Pagani

Davide Cantoni

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Memristive devices fabricated with silicon nanowire schottky barrier transistors.D. Sacchetto, M. Jamaa, S. Carrara, G. Micheli, and Y. Leblebici. ISCAS, page 9-12. IEEE, (2010)Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology.J. Sandrini, M. Barlas, M. Thammasack, T. Demirci, M. Marchi, D. Sacchetto, P. Gaillardon, G. Micheli, and Y. Leblebici. IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 339-351 (2016)Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review.D. Sacchetto, G. Micheli, and Y. Leblebici. Proc. IEEE, 100 (6): 2008-2020 (2012)Alternative design methodologies for the next generation logic switch.D. Sacchetto, M. Marchi, G. Micheli, and Y. Leblebici. ICCAD, page 231-234. IEEE Computer Society, (2011)Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.P. Gaillardon, L. Amarù, S. Bobba, M. Marchi, D. Sacchetto, Y. Leblebici, and G. Micheli. DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.D. Sacchetto, M. Jamaa, G. Micheli, and Y. Leblebici. ISCAS, page 1715-1718. IEEE, (2010)Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology.J. Sandrini, T. Demirci, M. Thammasack, D. Sacchetto, and Y. Leblebici. ISCAS, page 9-12. IEEE, (2015)GMS: Generic memristive structure for non-volatile FPGAs.P. Gaillardon, D. Sacchetto, S. Bobba, Y. Leblebici, and G. Micheli. VLSI-SoC, page 94-98. IEEE, (2012)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.S. Bobba, P. Gaillardon, J. Zhang, M. Marchi, D. Sacchetto, Y. Leblebici, and G. Micheli. NANOARCH, page 55-60. ACM, (2012)Towards structured ASICs using polarity-tunable Si nanowire transistors.P. Gaillardon, M. Marchi, L. Amarù, S. Bobba, D. Sacchetto, Y. Leblebici, and G. Micheli. DAC, page 123:1-123:4. ACM, (2013)

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Disambiguation of "Sacchetto, Davide"

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A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.

Please choose a person to relate this publication to

Davide Pennino

Davide Cadamuro

Davide Batic

Davide Pagani

Davide Cantoni

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sacchetto, Davide"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.

Please choose a person to relate this publication to

Davide Pennino

Davide Cadamuro

Davide Batic

Davide Pagani

Davide Cantoni

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.