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Accelerating Sparse Deep Neural Networks on FPGAs.

S. Huang, C. Pearson, R. Nagi, J. Xiong, D. Chen, and W. Hwu. HPEC, page 1-7. IEEE, (2019)

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Liu Deming

Deming Sun

Deming Kong

Chen Chen

Other publications of authors with the same name

Performance-driven mapping for CPLD architectures.D. Chen, J. Cong, M. Ercegovac, and Z. Huang. FPGA, page 39-47. ACM, (2001)Algorithm/Accelerator Co-Design and Co-Search for Edge AI.X. Zhang, Y. Li, J. Pan, and D. Chen. IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization.C. Gong, Y. Chen, Y. Lu, T. Li, C. Hao, and D. Chen. IEEE Trans. Computers, 70 (5): 696-710 (2021)ScaleHLS: Scalable High-Level Synthesis through MLIR.H. Ye, C. Hao, J. Cheng, H. Jeong, J. Huang, S. Neuendorffer, and D. Chen. CoRR, (2021)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation.K. Campbell, L. He, L. Yang, S. Gurumani, K. Rupnow, and D. Chen. DAC, page 7:1-7:6. ACM, (2016)Optimality study of resource binding with multi-Vdds.D. Chen, J. Cong, Y. Fan, and J. Xu. DAC, page 580-585. ACM, (2006)Throughput-oriented kernel porting onto FPGAs.A. Papakonstantinou, D. Chen, W. mei W. Hwu, J. Cong, and Y. Liang. DAC, page 11:1-11:10. ACM, (2013)Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.X. Liu, D. Kim, C. Wu, and D. Chen. SLIP@DAC, page 1:1-1:8. ACM, (2018)A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation.Y. Chen, A. Rogachev, A. Sangai, G. Iannaccone, G. Fiori, and D. Chen. DATE, page 1789-1794. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling.Y. Chen, M. Gholipour, and D. Chen. ASP-DAC, page 761-768. IEEE, (2016)

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Disambiguation of "Chen, Deming"

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Accelerating Sparse Deep Neural Networks on FPGAs.

Please choose a person to relate this publication to

Liu Deming

Deming Sun

Deming Kong

Deming Kong

Chen Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Deming"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Accelerating Sparse Deep Neural Networks on FPGAs.

Please choose a person to relate this publication to

Liu Deming

Deming Sun

Deming Kong

Deming Kong

Chen Chen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Accelerating Sparse Deep Neural Networks on FPGAs.