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An Architecture and an Interconnection Scheme for Time-Sliced Buses in Real-Time Processing., , and . RTSS, page 20-27. IEEE Computer Society, (1986)Embedded Fault-Tolerant Systems., , , and . IEEE Micro, 18 (5): 8-11 (1998)Guest Editors' Introduction., , and . IEEE Trans. Computers, 51 (2): 97-99 (2002)On the Constant Diagnosability of Baseline Interconnection Networks., and . IEEE Trans. Computers, 39 (12): 1485-1488 (1990)Measuring the timing jitter of ATE in the frequency domain., , , , , , , , , and . IEEE Trans. Instrumentation and Measurement, 55 (1): 280-289 (2006)Analysis and measurement of fault coverage in a combined ATE and BIST environment., , and . IEEE Trans. Instrumentation and Measurement, 53 (2): 300-307 (2004)A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates., , and . IEEE Trans. Instrumentation and Measurement, 58 (2): 401-410 (2009)Maximal diagnosis of interconnects of random access memories., , , and . IEEE Trans. Reliability, 52 (4): 423-434 (2003)Sequential diagnosis of processor array systems., , , and . IEEE Trans. Reliability, 53 (4): 487-498 (2004)A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM)., , and . ACM Great Lakes Symposium on VLSI, page 259-264. ACM, (2015)