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Reliability challenges for barrier/liner system in high aspect ratio through silicon vias., , , , , , , , , и . Microelectron. Reliab., 54 (9-10): 1949-1952 (2014)Analysis of microbump induced stress effects in 3D stacked IC technologies., , , , , , , , , и 9 other автор(ы). 3DIC, стр. 1-5. IEEE, (2011)Die to wafer 3D stacking for below 10um pitch microbumps., , , , , , , , , и 8 other автор(ы). 3DIC, стр. 1-4. IEEE, (2016)3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps., , , , , , , , , и 9 other автор(ы). ICICDT, стр. 1-4. IEEE, (2012)In-line metrology and inspection for process control during 3D stacking of IC's., , , , , , , и . 3DIC, стр. 1-4. IEEE, (2011)Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics., , , , , и . 3DIC, стр. TS7.2.1-TS7.2.4. IEEE, (2015)Extreme wafer thinning optimization for via-last applications., , , , , , , , , и 3 other автор(ы). 3DIC, стр. 1-5. IEEE, (2016)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , и 34 other автор(ы). VLSI Technology and Circuits, стр. 284-285. IEEE, (2022)Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN)., , и . VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)Process Complexity and Cost Considerations of Multi-Layer Die Stacks., , , , , , , , , и 5 other автор(ы). 3DIC, стр. 1-6. IEEE, (2019)