( en | de | ru )

 

Disambiguation of "Alam, Syed M."

Author of the publication

copydeleteadd this publication to your clipboard
Design tool and methodologies for interconnect reliability analysis in integrated circuits.

. Massachusetts Institute of Technology, Cambridge, MA, USA, (2004)ndltd.org (oai:dspace.mit.edu:1721.1/26722).

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Masoom Alam

Adnan Shahzad Syed

Renate Syed

Homayun Alam

Fakhrul Alam

 

Other publications of authors with the same name

Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (4): 647-658 (2011)STT-Based Non-Volatile Logic-in-Memory Framework., , and . Field-Coupled Nanocomputing, volume 8280 of Lecture Notes in Computer Science, Springer, (2014)Design tool and methodologies for interconnect reliability analysis in integrated circuits.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2004)ndltd.org (oai:dspace.mit.edu:1721.1/26722).Circuit Level Reliability Analysis of Cu Interconnects., , , and . ISQED, page 238-243. IEEE Computer Society, (2004)Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs., , and . ISQED, page 751-756. IEEE, (2011)Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs., , and . 3DIC, page 1-7. IEEE, (2009)Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis., , and . Microelectron. Reliab., 51 (2): 485-501 (2011)Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security., , and . IEEE Trans. Consumer Electron., 69 (1): 1-8 (February 2023)Non-destructive variability tolerant differential read for non-volatile logic., , and . MWSCAS, page 178-181. IEEE, (2012)Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 2008-2016 (2012)