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A region-based theory for state assignment in speed-independent circuits., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (8): 793-812 (1997)Coupling Asynchrony and Interrupts: Place Chart Nets., , , , , и . ICATPN, том 1248 из Lecture Notes in Computer Science, стр. 328-347. Springer, (1997)Quasi-Static Scheduling for Concurrent Architectures., , , и . ACSD, стр. 29-40. IEEE Computer Society, (2003)Exploiting area/delay tradeoffs in high-level synthesis., , , и . DATE, стр. 1024-1029. IEEE, (2012)Realistic performance-constrained pipelining in high-level synthesis., , , и . DATE, стр. 1382-1387. IEEE, (2011)Checking signal transition graph implementability by symbolic BDD traversal., , , , , и . ED&TC, стр. 325-332. IEEE Computer Society, (1995)Synthesis methodology for built-in at-speed testing., , и . ICCAD, стр. 183-188. IEEE Computer Society, (2005)Incremental high-level synthesis., , , , , , и . ASP-DAC, стр. 701-706. IEEE, (2010)Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis., , , , и . ASYNC, стр. 240-253. IEEE Computer Society, (1997)Task generation and compile-time scheduling for mixed data-control embedded software., , , , , , , и . DAC, стр. 489-494. ACM, (2000)