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A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing., , , , , , and . ISVLSI, page 107-112. IEEE Computer Society, (2007)A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing., , , , , , , and . IEICE Trans. Electron., 91-C (4): 543-552 (2008)Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes., , , , , , and . IEICE Trans. Electron., 90-C (10): 1949-1956 (2007)Fixed Point Data Type Modeling for High Level Synthesis., , , , and . IEICE Trans. Electron., 93-C (3): 361-368 (2010)A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection., , , , , and . VLSI Design, page 295-300. IEEE Computer Society, (2009)Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2695-2702 (2007)A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme., , , , , , , and . ISQED, page 659-663. IEEE Computer Society, (2009)Electronic structure around an As antisite near the (110) surface of GaAs, , , and . Physical Review B (Condensed Matter and Materials Physics), (xx xx 2005)10.1103/PhysRevB.71.125328.Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)A Dependable SRAM with 7T/14T Memory Cells., , , , , and . IEICE Trans. Electron., 92-C (4): 423-432 (2009)