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Efficient Backside Power Delivery for High-Performance Computing Systems.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1748-1756 (2022)

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Evolution of substrate noise generation mechanisms with CMOS technology scaling., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (2): 296-305 (2006)Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling., , , , , , and . EURASIP J. Wireless Comm. and Networking, (2006)Impact of technology scaling on substrate noise generation mechanisms mixed signal ICs., , , , , and . CICC, page 501-504. IEEE, (2004)Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter., , , , , and . DAC, page 452-457. ACM, (2000)A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS., , , , and . ISSCC, page 252-253. IEEE, (2008)A study on substrate noise coupling among TSVs in 3D chip stack., , , , and . IEICE Electron. Express, 15 (13): 20180460 (2018)A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 191-195 (2004)Design issues in heterogeneous 3D/2.5D integration., , , , , and . ASP-DAC, page 403-410. IEEE, (2013)A 12 bit 200 MHz low glitch CMOS D/A converter., , , , , , , , and . CICC, page 249-252. IEEE, (1998)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance., , , and . DATE, page 270-275. IEEE Computer Society, (2005)