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A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , и . IEEE J. Solid State Circuits, 54 (4): 1173-1184 (2019)A physical alpha-power law MOSFET model., , , , и . IEEE J. Solid State Circuits, 34 (10): 1410-1414 (1999)Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration., , и . IEEE J. Solid State Circuits, 37 (2): 183-190 (2002)Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)., , , и . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 899-912 (2001)A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 316-318. IEEE, (2019)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 174-175. IEEE, (2010)Circuit techniques for dynamic variation tolerance., , , , , , и . DAC, стр. 4-7. ACM, (2009)Welcome to ISQED 2013., , , , , , , и . ISQED, IEEE, (2013)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , и . VLSI Circuits, стр. 65-66. IEEE, (2018)Resilient microprocessor design for high performance & energy efficiency., , , , , , , , , и 1 other автор(ы). ISLPED, стр. 355-356. ACM, (2010)