( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Si interposer build-up options and impact on 3D system cost.

, , , и . 3DIC, стр. 1-5. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Emmanuelle Beyne

Dimitry Beynenson

Badrian Erich

Klaus Erichson

Freerk Erichsen

 

Другие публикации лиц с тем же именем

A study on substrate noise coupling among TSVs in 3D chip stack., , , , и . IEICE Electron. Express, 15 (13): 20180460 (2018)Design of Test Modules for the Analysis of MCM Interconnects., , и . ED&TC, стр. 614. IEEE Computer Society, (1996)Design issues in heterogeneous 3D/2.5D integration., , , , , и . ASP-DAC, стр. 403-410. IEEE, (2013)A novel concept for ultra-low capacitance via-last TSV., , , , , и . 3DIC, стр. 1-4. IEEE, (2010)In-tier diagnosis of power domains in 3D TSV ICs., , , , , , , , , и 1 other автор(ы). 3DIC, стр. 1-6. IEEE, (2011)Impact of 3D design choices on manufacturing cost., , , , и . 3DIC, стр. 1-5. IEEE, (2009)Active-lite interposer for 2.5 & 3D integration., , , , , , , , , и 5 other автор(ы). VLSIC, стр. 222-. IEEE, (2015)Constant Impedance Scaling Paradigm for Scaling LC transmission lines., , , , , , и . ISQED, стр. 387-392. IEEE Computer Society, (2006)Thermal experimental and modeling analysis of high power 3D packages., , , , , и . ICICDT, стр. 1-4. IEEE, (2015)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology., , , , , , , , , и 27 other автор(ы). IEEE J. Solid State Circuits, 46 (1): 293-307 (2011)