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Effects of Parameter Variations on Timing Characteristics of Clocked Registers., and . Journal of Circuits, Systems, and Computers, 18 (7): 1309-1320 (2009)110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules., , , , , , , , , and . ECOC, page 1-4. IEEE, (2021)3D integration: Circuit design, test, and reliability challenges., , , , , , , , and . IOLTS, page 217. IEEE Computer Society, (2010)Cost effectiveness of 3D integration options., , and . 3DIC, page 1-6. IEEE, (2010)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 46 (1): 293-307 (2011)Efficient Backside Power Delivery for High-Performance Computing Systems., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1748-1756 (2022)Buffer sizing for delay uncertainty induced by process variations., , and . ICECS, page 415-418. IEEE, (2004)SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links., , and . NETWORKING, volume 2345 of Lecture Notes in Computer Science, page 1233-1238. Springer, (2002)Si interposer build-up options and impact on 3D system cost., , , and . 3DIC, page 1-5. IEEE, (2013)Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers., and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 508-517. Springer, (2005)