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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 494-496. IEEE, (2018)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , и 12 other автор(ы). ISSCC, стр. 388-390. IEEE, (2019)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices., , , , , , , , , и 3 other автор(ы). VLSI Circuits, стр. 166-. IEEE, (2019)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , и . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (ноября 2023)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 52-64 (января 2024)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)