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Disambiguation of "Asanovic, Krste"

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AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads.

, , , , and . MICRO, page 62-76. ACM, (2023)

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FASED: FPGA-Accelerated Simulation and Evaluation of DRAM., , , , , , and . FPGA, page 330-339. ACM, (2019)Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology., , , and . International Conference on Supercomputing, page 340-347. ACM, (1997)Energy-aware lossless data compression., and . ACM Trans. Comput. Syst., 24 (3): 250-291 (2006)Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 723-730 (2015)Building Open Trusted Execution Environments., , , , and . IEEE Secur. Priv., 18 (5): 47-56 (2020)The GAP Benchmark Suite., , and . CoRR, (2015)An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (1): 140-152 (2022)A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET., , , , , , , , , and 9 other author(s). ESSCIRC, page 259-262. IEEE, (2021)FPGA Accelerated INDEL Realignment in the Cloud., , , , , , , , , and 2 other author(s). HPCA, page 277-290. IEEE, (2019)Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors., and . ISCA, page 336-345. IEEE Computer Society, (2005)