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Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits., , , , , и . ISCAS, стр. 1572-1575. IEEE, (1995)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems., , , , , и . SoCC, стр. 136-139. IEEE, (2014)Collaborative voltage scaling with online STA and variable-latency datapath., , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 347-352. ACM, (2010)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells., , , , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation., , , и . SoCC, стр. 5-10. IEEE, (2012)A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS., , , , , , и . A-SSCC, стр. 361-364. IEEE, (2014)Design of STR level converters for SoCs using the multi-island dual-VDD design technique., , , и . ISCAS, IEEE, (2006)Energy-efficient RISC design with on-demand circuit-level timing speculation., , , , и . ASP-DAC, стр. 477-478. IEEE, (2012)An ultra-low power interface CMOS IC design for biosensor applications., , , , , , , , , и 1 other автор(ы). MWSCAS, стр. 1196-1199. IEEE, (2012)A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 158-159. IEEE, (2013)