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Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.

T. Dhar, J. Poojary, Y. Li, K. Kunal, M. Madhusudan, A. Sharma, S. Manasi, J. Hu, R. Harjani, and S. Sapatnekar. ASP-DAC, page 158-163. ACM, (2021)

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Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays.N. Karmokar, A. Sharma, J. Poojary, M. Madhusudan, R. Harjani, and S. Sapatnekar. DATE, page 166-171. IEEE, (2022)The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu and 3 other author(s). ICCAD, page 54:1-54:2. IEEE, (2020)Reinforcing the Connection between Analog Design and EDA (Invited Paper).K. Kunal, M. Madhusudan, J. Poojary, S. Ramprasath, A. Sharma, R. Harjani, and S. Sapatnekar. ASPDAC, page 665-670. IEEE, (2024)Aging of Current DACs and its Impact in Equalizer Circuits.T. Dhar, J. Poojary, R. Harjani, and S. Sapatnekar. IRPS, page 1-6. IEEE, (2021)Machine Learning Techniques in Analog Layout Automation.T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu and 3 other author(s). ISPD, page 71-72. ACM, (2021)Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.T. Dhar, J. Poojary, Y. Li, K. Kunal, M. Madhusudan, A. Sharma, S. Manasi, J. Hu, R. Harjani, and S. Sapatnekar. ASP-DAC, page 158-163. ACM, (2021)Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.R. S, M. Madhusudan, A. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S. Burns, and S. Sapatnekar. ISPD, page 159-166. ACM, (2022)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.T. Dhar, R. S, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, and S. Sapatnekar. DATE, page 148-153. IEEE, (2022)Learning from Experience: Applying ML to Analog Circuit Design.K. Kunal, T. Dhar, Y. Li, M. Madhusudan, J. Poojary, A. Sharma, W. Xu, S. Burns, R. Harjani, J. Hu and 2 other author(s). ISPD, page 55. ACM, (2020)A general approach for identifying hierarchical symmetry constraints for analog circuit layout.K. Kunal, J. Poojary, T. Dhar, M. Madhusudan, R. Harjani, and S. Sapatnekar. ICCAD, page 120:1-120:8. IEEE, (2020)

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Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.

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Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.