( en | de | ru )

 

Disambiguation of "Ng, Yong-Gee"

Author of the publication

copydeleteadd this publication to your clipboard
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 48 (1): 150-158 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

ng-yong Yi

Kira Gee

Puangrat Yongvanit

Colin Gee

Michael Gee

 

Other publications of authors with the same name

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (1): 222-229 (2016)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology., , , , , , , , , and . ISSCC, page 376-377. IEEE, (2008)A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation., , , , , , , and . ISSCC, page 346-347. IEEE, (2010)A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation., , , , , , , and . IEEE J. Solid State Circuits, 46 (1): 76-84 (2011)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry., , , , , , , , and . ISSCC, page 230-232. IEEE, (2012)An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin., , , , , , , , and . IEEE J. Solid State Circuits, 34 (11): 1564-1570 (1999)A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management., , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 103-110 (2010)A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (1): 150-158 (2013)A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 148-154 (2009)