Author of the publication

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.

, , , , , , and . ITC, page 8. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing., , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)At-Speed Logic BIST Architecture for Multi-Clock Designs., , , , and . ICCD, page 475-478. IEEE Computer Society, (2005)Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). DFT, page 358-366. IEEE Computer Society, (2010)A Sequential Circuit Test Generation System., and . ITC, page 57-61. IEEE Computer Society, (1985)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)At-Speed Logic BIST for IP Cores., , , , , , , , and . DATE, page 860-861. IEEE Computer Society, (2005)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Des. Test Comput., 25 (2): 122-130 (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)Test compression and logic BIST at your fingertips., , , , and . ITC, page 2. IEEE Computer Society, (2005)Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard., , , , , , , , , and 6 other author(s). ITC, page 1-9. IEEE Computer Society, (2008)