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Disambiguation of "Bhoj, Ajay N."

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Gated-diode FinFET DRAMs: Device and circuit design-considerations.

, and . JETC, 6 (4): 12:1-12:32 (2010)

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Ajay Chavan

Godwin Olu Ajayi

Sanjay Bhojwani

Monika Bhojwani

 

Other publications of authors with the same name

Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (1): 47-58 (2013)Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology., and . ISQED, page 695-702. IEEE, (2011)Pragmatic design of gated-diode FinFET DRAMs., and . ICCD, page 390-397. IEEE Computer Society, (2009)Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 23 (3): 534-543 (2015)Gated-diode FinFET DRAMs: Device and circuit design-considerations., and . JETC, 6 (4): 12:1-12:32 (2010)Die-level leakage power analysis of FinFET circuits considering process variations., , and . ISQED, page 347-355. IEEE, (2010)Fault modeling for FinFET circuits., , and . NANOARCH, page 41-46. IEEE Computer Society, (2010)3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (11): 2094-2105 (2013)Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism., , , and . VLSID, page 300-305. IEEE Computer Society, (2016)Design of Efficient Content Addressable Memories in High-Performance FinFET Technology., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 963-967 (2015)