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Disambiguation of "Saligram, Rakshith"

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Cryogenic CMOS as an Enabler for Low Power Dynamic Logic.

, , and . ISLPED, page 1-6. IEEE, (2023)

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Other publications of authors with the same name

Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing., , , , , , , and . VLSI Technology and Circuits, page 302-303. IEEE, (2022)Cryogenic CMOS as an Enabler for Low Power Dynamic Logic., , and . ISLPED, page 1-6. IEEE, (2023)Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication., , , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 149-178. Springer, (2020)A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance., , , , and . CICC, page 1-2. IEEE, (2021)Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit., , , , and . CoRR, (2013)Towards the design of fault tolerant reversible circuits components of ALU using new PCMF gate., and . ICACCI, page 862-867. IEEE, (2013)CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications., , and . CICC, page 1-2. IEEE, (2021)A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration., , , and . VLSI-SOC, page 159-164. IEEE, (2020)Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4610-4618 (2022)Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG.. ISED, page 46-51. IEEE Computer Society, (2013)