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19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

, , , , , , , и . ISSCC, стр. 324-325. IEEE, (2016)

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Temmyo Ichiro

Ichiro Yamaguchi

Yuichi Fujimori

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Ichiro Tamura

 

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