( en | de | ru )

 

Disambiguation of "Kulkarni, Jaydeep P."

Author of the publication

copydeleteadd this publication to your clipboard
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design.

, and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 319-332 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jaydeep Belapure

Jagadish Kulkarni

Praveen Kulkarni

Aniket Kulkarni

Suchita Kulkarni

 

Other publications of authors with the same name

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (9): 1727-1730 (2011)Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 319-332 (2012)4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging., , , , , , and . ISSCC, page 1-3. IEEE, (2015)Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (1): 2-13 (2010)Thermal analysis of 8-T SRAM for nano-scaled technologies., , and . ISLPED, page 123-128. ACM, (2008)8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating., , , , , , , , and . ISSCC, page 152-153. IEEE, (2016)Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors., , and . ISCAS, page 1-5. IEEE, (2021)A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce., , , , , , and . CICC, page 1-2. IEEE, (2023)Aging Effects On Clock Gated Memory Phase Paths., , , and . DFT, page 1-5. IEEE, (2022)