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12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 210-211. IEEE, (2017)A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 270-271. IEEE, (2008)Isodelay output driver design using step-wise charging for low power., и . ESSCIRC, стр. 149-152. IEEE, (2005)Aggressor aware repeater circuits for improving on-chip bus performance and robustness., , и . ESSCIRC, стр. 261-264. IEEE, (2003)High speed current-mode signaling circuits for on-chip interconnects., , и . ISCAS (4), стр. 4138-4141. IEEE, (2005)New ECC for Crosstalk Impact Minimization., , , и . IEEE Des. Test Comput., 22 (4): 340-348 (2005)Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems., , , , и . IOLTS, стр. 135-140. IEEE Computer Society, (2004)Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication., , и . VLSI Design, стр. 325-329. IEEE Computer Society, (2005)Reducing Cross-Talk Induced Power Consumption and Delay., , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 179-188. Springer, (2004)Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity., , , и . ESSCIRC, стр. 323-326. IEEE, (2004)