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The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.

A. Vais, K. Martens, J. Franco, D. Lin, A. Alian, P. Roussel, S. Sioncke, N. Collaert, A. Thean, M. Heyns, G. Groeseneken, and K. Meyer. IRPS, page 5. IEEE, (2015)

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Lin Lin

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3DApe: A Real-Time 3D Audio Playback Engine.C. Jin, A. Kan, D. Lin, M. McGinity, K. Smith, T. Tan, and A. van Schaik. (May 2005)Real-time, head-tracked 3D audio with unlimited simultaneous soundsC. Jin, T. Tan, A. Kan, D. Lin, A. Schaik, K. Smith, and M. McGinity. (2005)Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application.S. Lung, D. Lin, S. Chen, G. Weng, C. Liu, S. Lai, C. Tsai, T. Wu, and R. Liu. CICC, page 479-482. IEEE, (2002)WS2 transistors on 300 mm wafers with BEOL compatibility.T. Schram, Q. Smets, B. Groven, M. Heyne, E. Kunnen, A. Thiam, K. Devriendt, A. Delabie, D. Lin, M. Lux and 8 other author(s). ESSDERC, page 212-215. IEEE, (2017)Tunnel FETs using Phosphorene/ReS2 heterostructures.Y. Balaji, Q. Smets, D. Lin, I. Asselberghs, I. Radu, and G. Groeseneken. DRC, page 113-114. IEEE, (2019)Towards high-performance polarity-controllable FETs with 2D materials.G. Resta, J. Gonzalez, Y. Balaji, T. Agarwal, D. Lin, F. Catthoor, I. Radu, G. Micheli, and P. Gaillardon. DATE, page 637-641. IEEE, (2018)Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures.C. Dou, D. Lin, A. Vais, T. Ivanov, H. Chen, K. Martens, K. Kakushima, H. Iwai, Y. Taur, A. Thean and 1 other author(s). Microelectron. Reliab., 54 (4): 746-754 (2014)Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures.Y. Balaji, Q. Smets, C. de la Rosa, A. Lu, D. Chiappe, T. Agarwal, D. Lin, C. Huyghebaert, I. Radu, D. Mocuta and 1 other author(s). ESSDERC, page 106-109. IEEE, (2017)The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.A. Vais, K. Martens, J. Franco, D. Lin, A. Alian, P. Roussel, S. Sioncke, N. Collaert, A. Thean, M. Heyns and 2 other author(s). IRPS, page 5. IEEE, (2015)Beyond-Si materials and devices for more Moore and more than Moore applications.N. Collaert, A. Alian, H. Arimura, G. Boccardi, G. Eneman, J. Franco, T. Ivanov, D. Lin, J. Mitard, S. Ramesh and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)

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Disambiguation of "Lin, Dennis"

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The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

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Disambiguation of "Lin, Dennis"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.