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Disambiguation of "Noda, Hideyuki"

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A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory.

, , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 853-861 (2007)

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Hideyuki Sakamoto

Teruhisa Noda

Tatsuhiko Noda

Shigeru Noda

Norihiro Noda

 

Other publications of authors with the same name

A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (10): 2363-2373 (2011)A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM., , , and . CICC, page 451-454. IEEE, (2005)A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 853-861 (2007)A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 88-C (10): 2020-2027 (2005)Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2017)3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV., , , , , , , , , and 2 other author(s). ISSCC, page 58-59. IEEE, (2017)CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table image coding example., , , , , , , and . ISCAS (5), page 5202-5205. IEEE, (2005)Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine., , , , , , , and . ISCAS, page 525-528. IEEE, (2007)The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 42 (1): 183-192 (2007)Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh., , , , , , , , and . IEICE Trans. Electron., 88-C (4): 622-629 (2005)