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Disambiguation of "Ipposhi, Takashi"

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A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory.

, , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 853-861 (2007)

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Takashi Seki

Takashi Iwata

Takashi Numaguchi

Takashi Tsuno

Takashi Ohtsuki

 

Other publications of authors with the same name

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI., , , , , and . CICC, page 429-432. IEEE, (2006)Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI., , , , , and . IEICE Electron. Express, 3 (21): 453-458 (2006)A 0.05�?0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory., , , , , , , and . ISSCC, page 482-483. IEEE, (2007)Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2691-2694 (2007)Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation., , , , , and . IEICE Trans. Electron., 90-C (4): 666-674 (2007)A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs., , , , , and . IEEE J. Solid State Circuits, 42 (11): 2611-2619 (2007)A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 853-861 (2007)Delayed-ABC SOI for crosstalk noise repair., , , , , , , and . IEICE Electron. Express, 5 (9): 354-360 (2008)A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control., , , , , and . IEICE Electron. Express, 6 (8): 456-460 (2009)A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI., , , , , , , , and . IEICE Trans. Electron., 90-C (4): 765-771 (2007)