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AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks.

, , and . ASP-DAC, page 529-538. IEEE, (1997)

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Equivalence checking of arithmetic circuits on the arithmetic bit level., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 586-597 (2004)Normalization at the arithmetic bit level., , and . DAC, page 457-462. ACM, (2005)Arithmetic Constraints in SAT-based Property Checking., , , and . MBMV, page 91-100. Shaker, (2007)Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation., , , , and . MBMV, page 1-4. VDE/IEEE, (2022)MetaFS: Model-driven Fault Simulation Framework., , , , , , and . DFT, page 1-4. IEEE, (2022)Symbolic quick error detection using symbolic initial state for pre-silicon verification., , , , , , and . DATE, page 55-60. IEEE, (2018)Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation., , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2022)Record & play: a structural fixed point iteration for sequential circuit verification., and . ICCAD, page 394-399. IEEE Computer Society / ACM, (1997)Logic optimization and equivalence checking by implication analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (3): 266-281 (1997)Towards the impact of state encoding on induction-based property checking., , and . MBMV, page 199-208. Shaker, (2003)