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Disambiguation of "Chang, Meng-Fan"

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Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.

, , , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1191-1205 (April 2024)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)
 

Other publications of authors with the same name

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques., , , , , , , , , and 2 other author(s). VLSIC, page 112-113. IEEE, (2012)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1657-1667 (2009)Crosstalk-insensitive via-programming ROMs using content-aware design framework., , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (6): 443-447 (2006)A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 52 (1): 218-228 (2017)Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)., , , and . IEEE J. Solid State Circuits, 55 (1): 3-5 (2020)A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (11): 2786-2798 (2016)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)