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Disambiguation of "Tachibana, Ryoichi"

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A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication.

, , , , , , , , , , , , , and . ISSCC, page 266-268. IEEE, (2012)

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Other publications of authors with the same name

30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology., , , , , , , , , and 49 other author(s). ISSCC, page 428-430. IEEE, (2021)20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication., , , , , , , , , and 10 other author(s). ISSCC, page 348-349. IEEE, (2014)A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS., , , , , and . ESSCIRC, page 472-475. IEEE, (2007)A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology., , , , , , , , , and 39 other author(s). IEEE J. Solid State Circuits, 55 (1): 178-188 (2020)Correction to Ä 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication"., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 48 (6): 1540 (2013)An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer., , , , , , , , , and 43 other author(s). ISSCC, page 442-444. IEEE, (2018)A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication., , , , , , , , , and 4 other author(s). ISSCC, page 266-268. IEEE, (2012)A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer., , , , , , , and . IEEE J. Solid State Circuits, 43 (4): 1030-1037 (2008)A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS., , , , , and . IEICE Trans. Electron., 92-C (6): 785-791 (2009)A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology., , , , , , , , , and 42 other author(s). ISSCC, page 210-212. IEEE, (2019)