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A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.

, , , , , , , , , , , , , , and . ISCAS, page 1588-1591. IEEE, (2014)

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A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme., , , , , , , and . IEICE Electron. Express, 11 (10): 20140297 (2014)Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs., , , and . CICC, page 355-358. IEEE, (2008)Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 57 (7): 2250-2262 (2022)10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications., , , , , , , , , and 4 other author(s). ISSCC, page 184-185. IEEE, (2014)A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS., , , , , , , , , and 1 other author(s). FPL, page 323-327. IEEE, (2020)A 16-Mb Toggle MRAM With Burst Modes., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 42 (11): 2378-2385 (2007)Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (2): 476-489 (2015)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory., , , , and . J. Multiple Valued Log. Soft Comput., 26 (1-2): 125-140 (2016)