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Disambiguation of "Bobba, Shashikanth"

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3.5-D integration: A case study.

, , , , and . ISCAS, page 2087-2090. IEEE, (2013)

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Vedik Bobba

Diwakar Bobbala

 

Other publications of authors with the same name

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture., and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2103-2115 (2015)Design of a novel type of on-chip transformer suitable for baluns in customary BICMOS/CMOS technologies., , , and . ECCTD, page 91-94. IEEE, (2005)GMS: Generic memristive structure for non-volatile FPGAs., , , , and . VLSI-SoC, page 94-98. IEEE, (2012)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors., , , , , , and . NANOARCH, page 55-60. ACM, (2012)Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors., , , and . DAC, page 42-47. ACM, (2012)Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement., , , , , , and . DAC, page 889-892. ACM, (2010)Towards structured ASICs using polarity-tunable Si nanowire transistors., , , , , , and . DAC, page 123:1-123:4. ACM, (2013)Synthesis of regular computational fabrics with ambipolar CNTFET technology., , , and . ICECS, page 70-73. IEEE, (2010)System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits., , , , , and . JETC, 10 (4): 33:1-33:19 (2014)CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits., , , , , , , and . ASP-DAC, page 336-343. IEEE, (2011)