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Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.

D. Pham, H. Anderson, E. Behnen, M. Bolliger, S. Gupta, H. Hofstee, P. Harvey, C. Johns, J. Kahle, A. Kameyama, J. Keaty, B. Le, S. Lee, T. Nguyen, J. Petrovick, M. Pham, J. Pille, S. Posluszny, M. Riley, J. Verock, J. Warnock, S. Weitzel, and D. Wendel. ASP-DAC, page 871-878. IEEE, (2006)

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Pille Urbas

Frank Pille

Ruth Pille

Wolfgang Pille

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A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction.A. Fritsch, M. Kugel, R. Sautter, D. Wendel, J. Pille, O. Torreiter, S. Kalyanasundaram, and D. Dobson. ESSCIRC, page 343-346. IEEE, (2015)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.C. Gonzalez, E. Fluhr, D. Dreps, D. Hogenmiller, R. Rao, J. Paredes, M. Floyd, M. Sperling, R. Kruse, V. Ramadurai and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.D. Pham, H. Anderson, E. Behnen, M. Bolliger, S. Gupta, H. Hofstee, P. Harvey, C. Johns, J. Kahle, A. Kameyama and 13 other author(s). ASP-DAC, page 871-878. IEEE, (2006)The circuit design of the synergistic processor element of a CELL processor.O. Takahashi, R. Cook, S. Cottier, S. Dhong, B. Flachs, K. Hirairi, A. Kawasumi, H. Murakami, H. Noro, H. Oh and 3 other author(s). ICCAD, page 111-117. IEEE Computer Society, (2005)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.E. Fluhr, J. Friedrich, D. Dreps, V. Zyuban, G. Still, C. Gonzalez, A. Hall, D. Hogenmiller, F. Malgioglio, R. Nett and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)A 32nm 0.5V-supply dual-read 6T SRAM.J. Kuang, J. Schaub, F. Gebara, D. Wendel, S. Saroop, T. Nguyen, T. Fröhnel, A. Müller, C. Durham, R. Sautter and 5 other author(s). CICC, page 1-4. IEEE, (2010)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.E. Fluhr, S. Baumgartner, D. Boerstler, J. Bulzacchelli, T. Diemoz, D. Dreps, G. English, J. Friedrich, A. Gattiker, T. Gloekler and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)

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Disambiguation of "Pille, Juergen"

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Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.

Please choose a person to relate this publication to

Pille Urbas

Frank Pille

Frank Pille

Ruth Pille

Wolfgang Pille

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Pille, Juergen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.

Please choose a person to relate this publication to

Pille Urbas

Frank Pille

Frank Pille

Ruth Pille

Wolfgang Pille

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.