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Disambiguation of "Bulzacchelli, John F."

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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)

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John F Rauthmann

F Georgi

F Schiemann

F Gütlbauer

F Himmel

 

Other publications of authors with the same name

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array., , , , , , , , , and 4 other author(s). OFC, page 1-3. IEEE, (2015)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS., , , , and . CICC, page 1-4. IEEE, (2019)A 25 Gb/s burst-mode receiver for low latency photonic switch networks., , , , , , , and . OFC, page 1-3. IEEE, (2015)A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS., , , , and . IEEE J. Solid State Circuits, 44 (12): 3526-3538 (2009)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology., , , , , , , , , and 15 other author(s). ISSCC, page 360-362. IEEE, (2022)Root cause identification of an hard-to-find on-chip power supply coupling fail., , , , , , and . ITC, page 1-7. IEEE Computer Society, (2012)Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration., , , , , , , , , and 1 other author(s). CICC, page 1-8. IEEE, (2024)Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates.. CICC, page 1-8. IEEE, (2013)