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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.

M. Marinella, S. Agarwal, A. Hsia, I. Richter, R. Jacobs-Gedrim, J. Niroula, S. Plimpton, E. Ipek, and C. James. CoRR, (2017)

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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.M. Marinella, S. Agarwal, A. Hsia, I. Richter, R. Jacobs-Gedrim, J. Niroula, S. Plimpton, E. Ipek, and C. James. CoRR, (2017)Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C.Q. Xie, M. Yuan, J. Niroula, B. Sikder, S. Luo, K. Fu, N. Rajput, A. Pranta, P. Yadav, Y. Zhao and 2 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Materials and Technology Issues for the Next Generation of Power Electronic Devices.A. Zubair, J. Niroula, N. Chowdhury, Y. Zhang, J. Lemettinen, and T. Palacios. DRC, page 1-2. IEEE, (2020)First Demonstration of GaN Vertical Power FinFETs on Engineered Substrate.A. Zubair, J. Perozek, J. Niroula, O. Aktas, V. Odnoblyudov, and T. Palacios. DRC, page 1-2. IEEE, (2020)Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.M. Marinella, S. Agarwal, A. Hsia, I. Richter, R. Jacobs-Gedrim, J. Niroula, S. Plimpton, E. Ipek, and C. James. IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 86-101 (2018)First Demonstration of GaN RF HEMTs on Engineered Substrate.P. Yadav, Q. Xie, J. Niroula, G. Micale, H. Pal, and T. Palacios. DRC, page 1-2. IEEE, (2023)Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator.R. Jacobs-Gedrim, S. Agarwal, K. Knisely, J. Stevens, M. van Heukelom, D. Hughart, J. Niroula, C. James, and M. Marinella. ICRC, page 1-10. IEEE, (2017)Using Floating Gate Memory to Train Ideal Accuracy Neural Networks.S. Agarwal, D. Garland, J. Niroula, R. Jacobs-Gedrim, A. Hsia, M. van Heukelom, E. Fuller, B. Draper, and M. Marinella. CoRR, (2019)

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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.

Please choose a person to relate this publication to

Horst John

Annemarie Johne

Hans-Dieter John

Walter John

Walter John

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Niroula, John"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.

Please choose a person to relate this publication to

Horst John

Annemarie Johne

Hans-Dieter John

Walter John

Walter John

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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Chicago
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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.